1. Field
Exemplary embodiments of the present invention relate to a delay circuit used for delaying a signal in various integrated circuits.
2. Description of the Related Art
A delay circuit (or shift circuit) refers to as a circuit which delays and outputs an input signal to control the timing of transmitting a signal. In particular, a variable delay circuit refers to a circuit which delays and outputs an input signal based on a preset or predetermined value. Since various integrated circuits operate in synchronization with their specific operation sequences and operation timings, the variable delay circuit having a variable delay value is widely used in the integrated circuits, e.g., semiconductor devices.
FIG. 1 is a block diagram of showing a configuration of a conventional delay circuit for single input signal.
Referring to FIG. 1, the delay circuit typically includes a delay unit which has a plurality of shifters 101 to 104 coupled in series and a selector 120 configured to select one of outputs FF1 to FFi of the shifters 101 to 104.
Each of the shifters 101 to 104 is configured to delay a signal inputted thereto by one clock in synchronization with a clock signal CLK, and the selector 120 is configured to select one of output signals FF1 to FFi of the shifters 101 to 104 and output selected signal as a final output signal OUT of the delay circuit. Therefore, the delay value of the delay circuit is determined depending on an output signal selected by the selector 120, wherein the output signal is selected among the output signals FF1 to FFi of the shifters 101 to 104.
Delay information SEL<1:i> inputted to the selector 120 is used in determining the output signal selected by the selector 120, wherein the output signal is selected among the output signals FF1 to FFi of the shifters 101 to 104. That is, the delay information SEL<1:i> is information indicating the delay value of the delay circuit.
FIG. 2 is a block diagram of showing a configuration of a conventional delay circuit for delaying a plurality of input signals, e.g., eight signals.
Referring to FIG. 2, the delay circuit of FIG. 2 includes eight delay units illustrated in FIG. 1. Since the number of input signals IN<0:7> to be delayed increases from one to eight, the area of the delay circuit also increases eight times. The total number of the shifters is obtained by multiplying the number of input signals and the maximum delay value of each of the input signals. For example, when the number of input signals to be delayed by the delay circuit is 10 and the maximum delay value supported by each of the delay units is 10 clocks, the delay circuit may be provided with 100 (10×10) shifters.
That is, according to the conventional delay circuit, the area of the delay circuit may increase in a geometric progression, as the number of input signals to be delayed by the delay circuit increases and the delay amount increases.